As electronic devices continue to reach higher levels of performance through among others shrinking feature sizes, greater integration and higher clock frequencies, manufacturers of testing devices have struggled to improve automatic test equipment (ATE) tester performance while also scaling the cost of the improved ATE testers with the technology. For example, ATE testers typically include hundreds or even thousands of test contacts or pins to test multiple devices under test (DUTs) in parallel. Each pin is connected to provide stimulus to a DUT and/or to receive a response of the DUT to the stimulus. One or more test resources, such as pattern generators, are connected to the pins to generate the stimulus and/or process the test results.
Traditionally, there has been a trade-off between the throughput achievable by the ATE testers and the cost of the ATE tester. For example, the cost of the ATE tester typically increases with the number and complexity of test resources. Therefore, to reduce the cost of ATE testers, a shared ATE architecture is commonly used to connect a single test resource, such as a pattern generator, to multiple DUTs. During testing, the pattern generator generates and simultaneously broadcasts a common test signal to each of the DUTs.
However, the test time for executing a particular test may vary between the DUTs in the batch of DUTs simultaneously tested by the ATE tester. Thus, in many testing applications, the test resource is required to poll the DUTs for confirmation that all of the DUTs have finished executing the current test before beginning the next test. Since a shared architecture requires that the test signal be synchronously broadcast to the DUTs, the test resource is unable to broadcast the next test signal until all DUTs indicate they are ready to receive the next test signal. For example, even if a particular DUT is ready to receive the next test signal in the current clock cycle, the test resource may be required to wait one or more additional clock cycles until all DUTs are ready to receive the next test signal before the test resource can transmit the next test signal to the DUTs.
Thus, a shared architecture may result in under-utilization of test resources, thereby decreasing test throughput. In addition, the test resource is usually capable of responding to only one DUT interrupt at a time. Therefore, test throughput in shared architectures is also adversely affected by the inability of the test resource to quickly respond to interrupts from DUTs.
An alternative to the shared resource architecture is a “per site” architecture, in which each DUT is tested by a dedicated test resource. Although the “per site” architecture significantly improves the throughput of the ATE tester, the increased cost associated with multiple test resources usually limits the benefits provided by the increase in test throughput. In addition, the normally high throughput of current “per site” testers is deteriorating due to the increased prevalence of varying pin counts in DUTs. For example, if a 32 pin-count tester resource is used to test an 8 pin-count DUT, under-utilization of pin resources occurs (i.e., only 25% of the pins are utilized). To limit the impact, the 32-pin count test resource can be used as a shared resource to simultaneously test four DUTs. However, this may result in the same under-utilization as the shared architecture discussed above.
In addition, some test systems require advanced algorithms for performing tasks related to testing, such as responding to DUT interrupts and repairing DUTs. These advanced processing algorithms are normally implemented in a master work station that is in communication with multiple test resources. As such, there is an added delay introduced by forwarding interrupts and repair requests to the work station and waiting for instructions from the work station. This added delay increases the latency of the test system, which effectively decreases the test throughput.
Therefore, what is needed is an ATE architecture that maximizes throughput while minimizing cost.